Experience: 6 years

Job Description:

• To be part of a highly skilled and challenging high speed PHY design team working on the latest technology nodes (12nm and below).
• Develop algorithms for DDR trainings, sub blocks such as data and address modules
• Responsible for all aspects of design and verification from spec to silicon along with interface design for controller and SoC.
• Active involvement in problem solving and implementing opportunities for improvement
• Mentoring and coaching other design team members on technical issues
• Pair with Analog designers to ensure smooth interface between Digital and Analog circuits